1. Field of the Invention
The present invention relates to a process for producing an especially planar semiconductor wafer with good nanotopology and a low-damage finish after machining, to a semiconductor wafer of this type, and to an apparatus for the double-side grinding of flat workpieces.
2. Background Art
Electronics, microelectronics and (micro)electromechanics require starting materials (substrates) with extremely high demands imposed on global and local flatness, thickness distribution, single surface referenced local flatness (nanotopology), roughness, and cleanliness. Depending on the intended use, the substrates used are wafers made from metals, insulators, or semiconductor material, in particular, compound semiconductors such as gallium arsenide, and primarily, elemental semiconductors such as silicon and sometimes germanium. Furthermore, the term semiconductor wafers is also to be understood as meaning substrates with artificially produced layer structures, such as for example silicon on silicon dioxide (SOI, silicon on insulator), preferably epitaxially produced silicon-germanium solid solutions (strained silicon), and silicon-germanium solid solutions on silicon dioxide (sSOI, strained SOI). For use in microelectronics in particular, semiconductor wafers have to have a particularly constant thickness, a global and local flatness, and must be smooth and clean.
The front surface (component surface) referenced flatness of semiconductor wafers within measurement windows, arranged on the surface of, for example 2 mm×2 mm or 10 mm×10 mm is reported in accordance with SEMI (Semiconductor Equipment and Materials International) as the “nanotopology”. Each new generation of components (design rule), defined on the basis of the smallest feature sizes which can still be produced in a defined and reproducible way, however, places increased demands on the nanotopology. Even at the present time, the demands for 130 nm, 90 nm and 65 nm generation features need to be satisfied.
According to prior art, silicon semiconductor wafers are produced in a large number of successive process steps, which can generally be divided into the following groups:    a) production of a single-crystal silicon ingot (crystal growth)    b) dividing the ingot into individual wafers (wafering, sawing)    c) mechanical machining    d) chemical machining    e) chemico-mechanical machining    f) if appropriate, coating
Furthermore, there are a large number of auxiliary steps, such as cleaning, classifying, measuring, packaging, etc., but these have no direct influence on the wafer flatness, or in particular on the nanotopology, and therefore are not considered in any more detail in the text which follows.
A single-crystal silicon ingot is usually produced by crucible pulling (Czochralski method). Furthermore, ingots with a diameter of <200 mm are also produced by float zone pulling (recrystallization of an ingot from polycrystalline silicon).
Preferred dividing processes include wire sawing (multi-wire slicing, MWS) with free grain (slurry MWS) or with bonded grain (Diamond wire MWS). Mechanical machining is used to remove sawing unevenness, to remove the surface layers whose crystallinity has been damaged by the relatively rough sawing processes or which have been contaminated by the sawing wire, and in particular for global leveling of the semiconductor wafers. In this context, sequential single-side grinding (SSG) and simultaneous double-side grinding (double-disk grinding, DDG) processes, as well as lapping and flat-honing, are used.
In the case of single-side grinding, the back surface of the semiconductor wafer is held on a chuck, while the front surface is leveled by a cup or, less often, by an outer grinding wheel, with the chuck and grinding wheel rotating and slowly being fed radially toward one another.
In the case of simultaneous double-side grinding, as described, for example, in EP-868 974A2, the semiconductor wafer is machined on both sides simultaneously while it is floating freely between two grinding wheels mounted on opposite, co-linear spindles, with axial guidance, substantially without any imposed forces, provided by a water cushion (hydrostatic principle) or air cushion (aerostatic principle) acting on the front surface and the back surface. The wafer is loosely prevented from floating off in the radial direction by a surrounding thin guide ring or individual radial spokes. The semiconductor wafer rotates about its axis of symmetry during grinding. This rotation is driven by friction wheels acting on the front surface and the back surface by a notch finger which engages the orientation notch in the semiconductor wafer, or by friction belts which are wrapped around part of the circumference of the semiconductor wafer. Precise orientation of the spindles with respect to one another (co-linearity) and of the center plane between the grinding wheels and the middle plane of the semiconductor wafer (co-planarity) are of particular importance to the success of DDG, with a view to achieving very good geometry and nanotopology values for the semiconductor wafer. Furthermore, the arrangement, pressure, thickness, through-flow rate and uniform shaping of the air or water cushions (hydro-pads) are particularly important. The apparatus for generating these air or water cushions may be arranged rigidly, in which case the decreasing thickness of the semiconductor wafer causes the thickness of the air or water cushions to increase during grinding, or may be adjusted during grinding, preferably controlled so as to achieve a constant thickness of the air or water cushions during the removal of material. To ensure precise orientation, a series of different measurement devices are used, monitoring the position of the semiconductor wafer and counteracting any asymmetry which may arise by axial displacement of the spindles. In addition, for absolute measurement of the position of the semiconductor wafer, the thickness of the wafer is also generally determined in situ by synchronous scanning of the front and back surfaces, and this measurement is used to control the grinding process steps (spindle feed) and in particular to terminate the process accurately at the required thickness.
The edge of the semiconductor wafer generally also has to be machined (edge rounding). Conventional grinding steps with profiled grinding wheels, belt grinding processes with continuous or periodic tool advance or integrated edge-rounding processes (edge grinding and polishing in one step) are used for this purpose.
The chemical machining steps comprise cleaning and etching steps, in particular for the removal of impurities, for the removal of damaged surface layers, and for reducing the surface roughness. Etching steps using alkaline media, in particular based on NaOH, KOH or tetramethylammonium hydroxide (TMAH); etching steps using acidic media, in particular based on mixtures of HNO3/HF; or combinations of these etching steps, are used during etching. In some cases, other etching processes such as plasma etching are also used.
The chemico-mechanical machining steps comprise polishing steps which smooth the surface, partially by chemical reaction and partially by mechanical removal of material (abrasion). In the case of single-side polishing (SSP), the back surface of the semiconductor wafer is held on a carrier plate using cement, vacuum, or adhesion during machining. In the case of double-side polishing (DSP), the semiconductor wafer is placed loosely in a thin, toothed disc and is polished on the front and back surface simultaneously in a “free-floating” position between an upper and a lower polishing plate covered with a polishing cloth. The polishing generally comprises one or more preliminary (material-removal polishing) and haze-free (finish polishing) polishing steps and if appropriate, also intermediate steps (buff polishing). The rough polishing can be carried out as single-wafer or multi-wafer SSP or DSP. For haze-free polishing, only SSP in the form of single-wafer polishing or multi-wafer polishing is used, on account of the higher frictional forces (softer polishing cloth).
Particularly demanding applications may require precision remachining of the semiconductor wafer in addition to the processes listed, so that any deviations in shape can be deliberately remachined at a local level. Examples of subaperture processes, as they are known, include plasma-assisted chemical etching (PACE) and related plasma etching processes, for example the jet-etch process. A relatively new subaperture process with considerable potential is magneto-rheological finishing (MRF), which is described in more detail, for example, in US2003/060020A1 and can be carried out as single-wafer or multi-wafer machining process. The MRF process uses a magneto-rheological liquid (ferro-fluid), the viscosity of which increases in the magnetic field by up to many orders of magnitude as a function of the field strength, for the local removal of material. This allows local production of a rigid (magnetically “thickened”) “grinding tool” which can be used to grind the surface of the semiconductor wafer. The flatnesses which can be achieved with the MRF process are superior to those of polishing by up to one order of magnitude, albeit with a much greater machining outlay (cycle time).
It is preferable for multi-stage material-removing mechanical machining steps to be used to produce especially flat semiconductor wafers with a good nanotopology. By way of example, U.S. Pat. No. 5,942,445 describes a process which comprises a sequence made up of a first, rough grinding step in a first grinding machine, with DDG preferably being used, followed by sequential SSG of both sides using a finishing grinding wheel in a second grinding machine. However, this multi-stage process sequence is complex, relatively inflexible, and overall requires very large amounts of material to be removed on account of repeated grinding operations. In particular, however, the SSG largely destroys the advantages of the preceding DDG.
U.S. Pat. No. 6,066,565 describes a process sequence involving a two-stage mechanical planarization step, in which the rounding of the edge of the semiconductor wafer is carried out between the first mechanical planarization step and the second mechanical planarization step and in which the two planarization steps are in each case selected independently from a whole group of proposed mechanical machining processes. The group includes DDG, SSG, lapping and plasma etching. This process sequence is likewise complex, material-intensive, susceptible to faults, and expensive.